EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 80

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.5.3 RMU_CMD - Command Register
3
2
1
0
31:1
0
Bit
Offset
0x008
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
EXTRST
Set if an external pin reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 76) for details on how to
interpret this bit.
BODREGRST
Set if a regulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 76)
for details on how to interpret this bit.
BODUNREGRST
Set if a unregulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p.
76) for details on how to interpret this bit.
PORST
Set if a power on reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 76) for details on how to interpret
this bit.
Reserved
RCCLR
Set this bit to clear the LOCKUPRST and SYSREQRST bits in the RMU_RSTCAUSE register. Use the HRCCLR bit in the
EMU_AUXCTRL register to clear the remaining bits.
Name
Name
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
R
W1
Access
Access
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Bit Position
80
External Pin Reset
Brown Out Detector Regulated Domain Reset
Brown Out Detector Unregulated Domain Reset
Power On Reset
Reset Cause Clear
Description
Description
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