EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 199

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13
12
11
10
9
8
7
6:5
4
3
Bit
2010-09-06 - d0001_Rev1.00
RXINV
Setting this bit will invert the input to the USART receiver.
TXBIL
Determines the interrupt and status level of the transmit buffer.
CSMA
This register determines the action to be performed when slave-select is configured as an input and driven low while in master mode.
MSBF
Decides whether data is sent with the least significant bit first, or the most significant bit first.
CLKPHA
Determines where data is set-up and sampled according to the bus clock when in synchronous mode.
CLKPOL
Determines the clock polarity of the bus clock used in synchronous mode.
Reserved
OVS
Sets the number of clock periods in a UART bit-period. More clock cycles gives better robustness, while less clock cycles gives
better performance.
MPAB
Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame
as a multi-processor address frame.
MPM
Name
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Value
0
1
2
3
Mode
EMPTY
HALFFULL
Mode
NOACTION
GOTOSLAVEMODE
Mode
SAMPLELEADING
SAMPLETRAILING
Mode
IDLELOW
IDLEHIGH
Mode
X16
X8
X6
X4
Description
Output from the transmitter is passed unchanged to U(S)n_TX
Output from the transmitter is inverted before it is passed to U(S)n_TX
Description
Input is passed directly to the receiver
Input is inverted before it is passed to the receiver
Description
Data is sent with the least significant bit first
Data is sent with the most significant bit first
0
0
0
0
0
0
0x0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Description
TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty.
TXBL is cleared when the buffer becomes nonempty.
TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty.
TXBL is cleared when the buffer becomes full.
Description
No action taken
Go to slave mode
Description
Data is sampled on the leading edge and set-up on the trailing edge of the bus clock
in synchronous mode
Data is set-up on the leading edge and sampled on the trailing edge of the bus clock
in synchronous mode
Description
The bus clock used in synchronous mode has a low base value
The bus clock used in synchronous mode has a high base value
Description
Regular UART mode with 16X oversampling in asynchronous mode
Double speed with 8X oversampling in asynchronous mode
6X oversampling in asynchronous mode
Quadruple speed with 4X oversampling in asynchronous mode
...the world's most energy friendly microcontrollers
199
Receiver Input Invert
TX Buffer Interrupt Level
Action On Slave-Select In Master Mode
Most Significant Bit First
Clock Edge For Setup/Sample
Clock Polarity
Oversampling
Multi-Processor Address-Bit
Multi-Processor Mode
Description
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