EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 156

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.9.1 Slave State Machine
15.3.9.2 Address Recognition
15.3.9.3 Slave Transmitter
2010-09-06 - d0001_Rev1.00
The slave state machine is shown in Figure 15.11 (p. 156) . The dotted lines show where I
interrupt flags are set. The full-drawn circles show places where interaction may be required by software
to let the transmission proceed.
Figure 15.11. I
The I
not fully automatic, but can be assisted by the 7-bit address comparator as shown in Section 15.3.11 (p.
160) . Address recognition is supported in all energy modes.
The slave address, i.e. the address which the I
the I2Cn_SADDR register. In addition to the address, a mask must be specified, telling the address
comparator which bits of an incoming address to compare with the address defined in I2Cn_SADDR.
The mask is defined in I2Cn_SADDRMASK, and for every zero in the mask, the corresponding bit in
the slave address is treated as a don’t-care.
An incoming address that fails address recognition is automatically replied to with a NACK. Since only
the bits defined by the mask are checked, a mask with a value 0x00 will result in all addresses being
accepted. A mask with a value 0x7F will only match the exact address defined in I2Cn_SADDR, while
a mask 0x70 will match all addresses where the three most significant bits in I2Cn_SADDR and the
incoming address are equal.
If GCAMEN in I2Cn_CTRL is set, the general call address is always accepted regardless of the result
of the address recognition. The start-byte, i.e. the general call address with the R/W bit set is ignored
unless it is included in the defined slave address.
When an address is accepted by the address comparator, the decision of whether to ACK or NACK the
address is passed to software.
When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated
START conditions are detected. No interaction is required on this event however.
0/1
Received from m aster
2
Transm itted by self
C module provides automatic address recognition for 7-bit addresses. 10-bit address recognition is
Bus state/event
Interaction required. Clock-
stretching applied until
m anual or autom atic
interaction has been
perform ed
Idle/busy
Interrupt flag set
2
C Slave State Machine
Bus state (STATE)
Go to state
S
ADDR R
ADDR W
Slave transm itter
Slave receiver
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156
2
73
71
C module should be addressed with, is defined in
A
N
A
N
DATA
DATA
B1
N
A
Arb. lost
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A
N
DD
D5
X
Arb. lost
Sr
Sr
P
P
2
C-specific
41
41
0
1
0
1