EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 371

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.5.4 DACn_CH1CTRL - Channel 1 Control Register
1
0
31:7
6:4
3
2
1
0
Bit
Offset
0x00C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Select Channel 0 conversion trigger.
REFREN
Set to enable automatic refresh of channel 0. Refresh period is set by REFRSEL in DACn_CTRL.
EN
Enable/disable channel 0.
Reserved
PRSSEL
Select Channel 1 PRS input channel.
Reserved
PRSEN
Select Channel 1 conversion trigger.
REFREN
Set to enable automatic refresh of channel 1. Refresh period is set by REFRSEL in DACn_CTRL.
EN
Name
Name
Value
0
1
Value
0
1
Value
0
1
2
3
4
5
6
7
Value
0
1
Value
0
1
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
Description
Channel 0 is triggered by CH0DATA or COMBDATA write
Channel 0 is triggered by PRS input
Description
Channel 0 is not refreshed automatically
Channel 0 is refreshed automatically
Description
Channel 1 is triggered by CH1DATA or COMBDATA write
Channel 1 is triggered by PRS input
Description
Channel 1 is not refreshed automatically
Channel 1 is refreshed automatically
0
0
0x0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Access
Description
PRS ch 0 triggers channel 1 conversion.
PRS ch 1 triggers channel 1 conversion.
PRS ch 2 triggers channel 1 conversion.
PRS ch 3 triggers channel 1 conversion.
PRS ch 4 triggers channel 1 conversion.
PRS ch 5 triggers channel 1 conversion.
PRS ch 6 triggers channel 1 conversion.
PRS ch 7 triggers channel 1 conversion.
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371
Bit Position
Channel 0 Automatic Refresh Enable
Channel 0 Enable
Channel 1 PRS Trigger Select
Channel 1 PRS Trigger Enable
Channel 1 Automatic Refresh Enable
Channel 1 Enable
Description
Description
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