EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 164

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14
13:12
11:10
9:8
7
6
5
4
3
2
Bit
2010-09-06 - d0001_Rev1.00
When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated.
Reserved
BITO
Use to generate a timeout when SCL has been high for a given amount time between a START and STOP condition. When in a
bus transaction, i.e. the BUSY flag is set, a timer is started whenever SCL goes high. When the timer reaches the value defined
by BITO, it sets the BITO interrupt flag. The BITO interrupt flag will then be set periodically as long as SCL remains high. The bus
idle timeout is active as long as BUSY is set. It is thus stopped automatically on a timeout if GIBITO is set. It is also stopped a
STOP condition is detected and when the ABORT command is issued. The timeout is activated whenever the bus goes BUSY, i.e.
a START condition is detected.
Reserved
CLHR
Determines the ratio between the low and high parts of the clock signal generated on SCL as master.
Reserved
GCAMEN
Set to enable address match on general call in addition to the programmed slave address.
ARBDIS
A master or slave will not release the bus upon losing arbitration.
AUTOSN
Write to 1 to make a master transmitter send a STOP when a NACK is received from a slave.
AUTOSE
Write to 1 to make a master transmitter send a STOP when no more data is available for transmission.
AUTOACK
Set to enable automatic acknowledges.
Name
Value
0
1
Value
0
1
2
3
Value
0
1
2
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Mode
OFF
40PCC
80PCC
160PCC
Mode
STANDARD
ASYMMETRIC
FAST
Description
A bus idle timeout has no effect on the bus state.
A bus idle timeout tells the I
Description
General call address will be NACK'ed if it is not included by the slave address and address mask.
When a general call address is received, a software response is required.
Description
When a device loses arbitration, the ARB interrupt flag is set and the bus is released.
When a device loses arbitration, the ARB interrupt flag is set, but communication proceeds.
Description
Stop is not automatically sent if a NACK is received from a slave.
The master automatically sends a STOP if a NACK is received from a slave.
Description
A stop must be sent manually when no more data is to be transmitted.
The master automatically sends a STOP when no more data is available for transmission.
0x0
0x0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
Access
2
C module that the bus is idle, allowing new transfers to be initiated.
Description
Timeout disabled
Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in
a 50us timeout.
Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in
a 100us timeout.
Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results
in a 200us timeout.
Description
The ratio is 4:4. Both low and high periods lasts 4 prescaled clock cycles
The ratio is 6:3. Low period lasts 6 and high period lasts 4 prescaled clock cycles
The ratio is 11:6. Low period lasts 16 and high period lasts 9 prescaled clock cycles
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164
Bus Idle Timeout
Clock Low High Ratio
General Call Address Match Enable
Arbitration Disable
Automatic STOP on NACK
Automatic STOP when Empty
Automatic Acknowledge
Description
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