EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 45

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.2.3.5 Memory scatter-gather
2010-09-06 - d0001_Rev1.00
Task B
After task B completes, the host processor can configure the alternate data structure for task D.
After the controller receives a new request for the channel and it has the highest priority then task C
commences:
Task C
After task C completes, the host processor can configure the primary data structure for task E.
After the controller receives a new request for the channel and it has the highest priority then task D
commences:
Task D
After the controller receives a new request for the channel and it has the highest priority then task E
commences:
Task E
If the controller receives a new request for the channel and it has the highest priority then it attempts to
start the next task. However, because the host processor has not configured the alternate data structure,
and on completion of task D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA
transaction completes.
Note
In memory scatter-gather mode the controller receives an initial request and then performs four DMA
transfers using the primary data structure. After this transfer completes, it starts a DMA cycle using the
7. The controller performs four DMA transfers.
8. The controller arbitrates. After the controller receives a request for this channel, the flow
9. The controller performs four DMA transfers.
10. T he controller arbitrates. After the controller receives a request for this channel, the flow
11. T he controller performs the remaining four DMA transfers.
12. T he controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
13. T he controller performs two DMA transfers.
14. T he controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
15. T he controller performs four DMA transfers.
16. T he controller arbitrates. After the controller receives a request for this channel, the flow
17. T he controller performs the remaining DMA transfer.
18. T he controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
19. T he controller performs four DMA transfers.
20. T he controller arbitrates. After the controller receives a request for this channel, the flow
21. T he controller performs the remaining three DMA transfers.
22. T he controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
You can also terminate the ping-pong DMA cycle in Figure 8.3 (p. 44) , if you configure
task E to be a basic DMA cycle by setting the cycle_ctrl field to 3’b001.
continues if the channel has the highest priority.
continues if the channel has the highest priority.
arbitration process.
arbitration process.
continues if the channel has the highest priority.
arbitration process.
continues if the channel has the highest priority.
arbitration process.
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