EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 201

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.3 USARTn_TRIGCTRL - USART Trigger Control register
7:4
3:0
31:6
5
4
3
2:0
Bit
Offset
0x008
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
DATABITS
This register sets the number of data bits in a USART frame.
Reserved
TXTEN
When set, the PRS channel selected by TSEL sets TXEN, enabling the transmitter on positive trigger edges.
RXTEN
When set, the PRS channel selected by TSEL sets RXEN, enabling the receiver on positive trigger edges.
Reserved
TSEL
Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and TXTEN.
Name
Name
Value
1
2
3
4
5
6
7
8
9
10
11
12
13
Value
0
1
2
3
4
5
6
7
Mode
FOUR
FIVE
SIX
SEVEN
EIGHT
NINE
TEN
ELEVEN
TWELVE
THIRTEEN
FOURTEEN
FIFTEEN
SIXTEEN
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
0x5
0
0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
Access
Access
Description
Each frame contains 4 data bits
Each frame contains 5 data bits
Each frame contains 6 data bits
Each frame contains 7 data bits
Each frame contains 8 data bits
Each frame contains 9 data bits
Each frame contains 10 data bits
Each frame contains 11 data bits
Each frame contains 12 data bits
Each frame contains 13 data bits
Each frame contains 14 data bits
Each frame contains 15 data bits
Each frame contains 16 data bits
Description
PRS Channel 0 selected
PRS Channel 1 selected
PRS Channel 2 selected
PRS Channel 3 selected
PRS Channel 4 selected
PRS Channel 5 selected
PRS Channel 6 selected
PRS Channel 7 selected
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201
Bit Position
Data-Bit Mode
Transmit Trigger Enable
Receive Trigger Enable
Trigger PRS Channel Select
Description
Description
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