EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 435

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

31:24
23:18
17:16
15:9
8
7
6:5
4:3
2
1
Offset
0x00C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
FCTOP
These bits contain the Top Value for the Frame Counter: CLK
FCPRESC
These bits controls the prescaling value for the Frame Counter input clock.
Reserved
FCEN
When this bit is set, the frame counter is enabled.
ALOGSEL
When this bit is set, the animation registers are AND'ed together. When this bit is cleared, the animation registers are OR'ed together.
AREGBSC
These bits controls the shift operation that is performed on Animation register B.
AREGASC
These bits controls the shift operation that is performed on Animation register A.
AEN
When this bit is set, the animate function is enabled.
BLANK
When this bit is set, all segment output waveforms are configured to blank the LCD display. The Segment Data Registers are not
affected when writing this bit.
Name
Value
0
1
2
3
Value
0
1
Value
0
1
2
Value
0
1
2
Value
0
1
Mode
DIV1
DIV2
DIV4
DIV8
Mode
AND
OR
Mode
NOSHIFT
SHIFTLEFT
SHIFTRIGHT
Mode
NOSHIFT
SHIFTLEFT
SHIFTRIGHT
Description
Display is not "blanked"
Display is "blanked"
0x00
0x0
0
0
0x0
0x0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
Access
Description
CLK
CLK
CLK
CLK
Description
AREGA and AREGB AND'ed
AREGA and AREGB OR'ed
Description
No Shift operation on Animation Register B
Animation Register B is shifted left
Animation Register B is shifted right
Description
No Shift operation on Animation Register A
Animation Register A is shifted left
Animation Register A is shifted right
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435
Bit Position
FC
FC
FC
FC
EVENT
Frame Counter Top Value
Frame Counter Prescaler
= CLK
= CLK
= CLK
= CLK
Frame Counter Enable
Animate Logic Function Select
Animate Register B Shift Control
Animate Register A Shift Control
Animation Enable
Blank Display
Description
FRAME
FRAME
FRAME
FRAME
= CLK
/ 1
/ 2
/ 4
/ 8
FC
/ (1 + FCTOP[5:0]).
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