EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 427

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

29.3.8 Data Update
29.3.9 Frame Counter (FC)
2010-09-06 - d0001_Rev1.00
Table 29.9. LCD Framerate Conversion Table
Table settings: Min: FDIV = 7, Max: FDIV = 0
The LCD Driver logic that controls the output waveforms is clocked on LFACLK
Control Registers are clocked on the HFCORECLK. To avoid metastability and unpredictable behavior,
the data in the Segment Data (SEGDn) registers must be synchronized to the LCD driver logic. Also,
it is important that data is updated at the beginning of an LCD frame since the segment waveform
depends on the segment data and a change in the middle of a frame may lead to a DC-component in that
frame. The LCD driver has dedicated functionality to synchronize data transfer to the LCD frames. The
synchronization logic is applied to all data that need to be updated at the beginning of the LCD frames:
• LCD_SEGDn
• LCD_AREGA
• LCD_AREGB
• LCD_BACTRL
The different methods to update data are controlled by the UDCTRL bits in LCD_CTRL.
Table 29.10. LCD Update Data Control (UDCTRL) Bits
The Frame Counter is synchronized to the LCD frame start and will generate an event after a
programmable number of frames. An FC event can trigger:
• LCD ready interrupt
• Blink (controlling the blink frequency)
• Next state in the Animation State Machine
• Data update if UDCTRL = 01
The Frame Counter is a down counter. It is enabled by writing FCEN in LCD_BACTRL. Optionally, the
Frame Counter can be prescaled so that the Frame Counter is decremented at:
Static
Duplex
Triplex
Quadruplex
UDCTRL
00
01
10
MUX Mode
LFACLK
LFACLK
LFACLK
LFACLK
Frame- rate
Mode
REGULAR
FCEVENT
FRAMESTART
formula
LCD
LCD
LCD
LCD
/2
/4
/6
/8
LFACLK
kHz
Min
128
64
43
32
LCDpre
Max
1024
512
341
256
Description
The data transfer is controlled by SW and data synchronization is
initiated by writing data to the buffers. Data is transferred as soon as
possible, possibly creating a frame with a DC component on the LCD.
The data transfer is done at the next event triggered by the Frame
Counter (FC). See Section 29.3.9 (p. 427) for details on how to
configure the Frame Counter. Optionally, the Frame Counter can also
generate an interrupt at every event.
The data transfer is done at frame-start.
= 2
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427
LFACLK
kHz
Min
64
32
21
16
Resulting Framerate, CLK
LCDpre
Max
512
256
171
128
= 1
LFACLK
0.5 kHz
Min
32
16
11
8
FRAME
LCDpre
Max
256
128
85
64
LCDpre
www.energymicro.com
(Hz)
=
. The LCD data and
LFACLK
0.25 kHz
Min
16
8
5
4
LCDpre
Max
128
64
43
32
=