EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 58

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-09-06 - d0001_Rev1.00
Example 8.1. DMA Transfer
1. Configure the channel select for using USART1 with DMA channel 0
2. Configure the primary channel descriptor for DMA channel 0
3. Enable the DMA
4. Disable the single requests for channel 0 (i.e. do not react to data available, wait for buffer full)
5. Enable buffer-full requests for channel 0
6. 6. Use the primary data structure for channel 0
7. 7. Enable channel 0
a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0
a. Write XX (read address of USART1) to src_data_end_ptr
b. Write 0x20003420 + 40 to dst_data_end_ptr c
c. Write these values to channel_cfg for channel 0:
a. Write EN=1 to DMA_CONFIG
a. Write DMA_CHUSEBURSTS[0]=1
a. Write DMA_CHREQMASKC[0]=1
a. Write DMA_CHALTC[0]=1
a. Write DMA_CHENS[0]=1
i. dst_inc=b01 (destination halfword address increment)
ii. dst_size=b01 (halfword transfer size)
iii. src_inc=b11 (no address increment for source)
iv. src_size=01 (halfword transfer size)
v. dst_prot_ctrl=000 (no cache/buffer/privilege)
vi. src_prot_ctrl=000 (no cache/buffer/privilege)
vii.R_power=b0000 (arbitrate after each DMA transfer)
viii. n _minus_1=d20 (transfer 21 halfwords)
ix. next_useburst=b0 (not applicable)
x. cycle_ctrl=b001 (basic operating mode)
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