EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 187

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.3.2.6.3 Two Data-links
16.3.2.7 Large Frames
2010-09-06 - d0001_Rev1.00
The USn_CS output is active low by default, but its polarity can be changed with CSINV in
USARTn_CTRL. AUTOCS works regardless of which mode the USART is in, so this functionality can
also be used for automatic chip/slave select when in synchronous mode (e.g. SPI).
Some limited devices only support half duplex communication even though two data links are available.
In this case software is responsible for making sure data is not transmitted when incoming data is
expected.
As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the
buffers are combined when working with USART-frames of 10 or more data bits.
To transmit such a frame, at least two elements must be available in the transmit buffer. If only one
element is available, the USART will wait for the second element before transmitting the combined frame.
Both the elements making up the frame are consumed when transmitting such a frame.
When using large frames, the 9th bits in the buffers are unused. For an 11 bit frame, the 8 least significant
bits are thus taken from the first element in the buffer, and the 3 remaining bits are taken from the second
element as shown in Figure 16.9 (p. 187) . The first element in the transmit buffer, i.e. element 0 in
Figure 16.9 (p. 187) is the first element written to the FIFO, or the least significant byte when writing
two bytes at a time using USARTn_TXDOUBLE.
Figure 16.9. USART Transmission of Large Frames
As shown in Figure 16.9 (p. 187) , frame transmission control bits are taken from the second element
in FIFO.
The two buffer elements can be written at the same time using the USARTn_TXDOUBLE or
USARTn_TXDOUBLEX register. The TXDATAX0 bitfield then refers to buffer element 0, and
TXDATAX1 refers to buffer element 1.
TX buffer elem ent 1
TX buffer elem ent 0
Shift register
0
1
2
3
4
5
6
0
0
1
7
1
Peripheral Bus
2
0
2
1
3
2
4
5
6
7
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187
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