EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 263

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.5.5 TIMERn_IF - Interrupt Flag Register
31:11
10
9
8
7
6
5
4
3:2
1
0
31:11
10
9
8
7
6
5
Bit
Offset
0x010
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
ICBOF2
Enable/disable Compare/Capture ch 2 input capture buffer overflow interrupt.
ICBOF1
Enable/disable Compare/Capture ch 1 input capture buffer overflow interrupt.
ICBOF0
Enable/disable Compare/Capture ch 0 input capture buffer overflow interrupt.
Reserved
CC2
Enable/disable Compare/Capture ch 2 interrupt.
CC1
Enable/disable Compare/Capture ch 1 interrupt.
CC0
Enable/disable Compare/Capture ch 0 interrupt.
Reserved
UF
Enable/disable underflow interrupt.
OF
Enable/disable overflow interrupt.
Reserved
ICBOF2
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC2_CCV/TIMERn_CC2_CCVB register
pair.
ICBOF1
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC1_CCV/TIMERn_CC1_CCVB register
pair.
ICBOF0
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC0_CCV/TIMERn_CC0_CCVB register
pair.
Reserved
CC2
This bit indicates that there has been an interrupt event on Compare/Capture channel 2.
CC1
Name
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
Access
Access
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263
Bit Position
CC Channel 2 Input Capture Buffer Overflow Interrupt Enable
CC Channel 1 Input Capture Buffer Overflow Interrupt Enable
CC Channel 0 Input Capture Buffer Overflow Interrupt Enable
CC Channel 2 Interrupt Enable
CC Channel 1 Interrupt Enable
CC Channel 0 Interrupt Enable
Underflow Interrupt Enable
Overflow Interrupt Enable
CC Channel 2 Input Capture Buffer Overflow Interrupt Flag
CC Channel 1 Input Capture Buffer Overflow Interrupt Flag
CC Channel 0 Input Capture Buffer Overflow Interrupt Flag
CC Channel 2 Interrupt Flag
CC Channel 1 Interrupt Flag
Description
Description
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