EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 181

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.3.2.3.2 Frame Transmission Control
2010-09-06 - d0001_Rev1.00
frames, complete with control bits to be written at once. When data is written to the transmit buffer
using USARTn_TXDATAX and USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override
the value in BIT8DV in USARTn_CTRL, and alone define the 9th bits that are transmitted if 9-bit
frames are used. Figure 16.3 (p. 181) shows the basics of the transmit buffer when DATABITS in
USARTn_FRAME is configured to less than 10 bits.
Figure 16.3. USART Transmit Buffer Operation
When writing more frames to the transmit buffer than there is free space for, the TXOF interrupt flag in
USARTn_IF will be set, indicating the overflow. The data already in the transmit buffer is preserved in
this case, and no data is written.
In addition to the interrupt flag TXC in USARTn_IF and status flag TXC in USARTn_STATUS which are
set when the transmitter is idle, TXBL in USARTn_STATUS and the TXBL interrupt flag in USARTn_IF
are used to indicate the level of the transmit buffer. TXBIL in USARTn_CTRL controls the level at which
these bits are set. If TXBIL is cleared, they are set whenever the transmit buffer becomes empty, and if
TXBIL is set, they are set whenever the transmit buffer goes from full to half-full or empty. Both the TXBL
status flag and the TXBL interrupt flag are cleared automatically when their condition becomes false
The transmit buffer, including the transmit shift register can be cleared by setting CLEARTX in
USARTn_CMD. This will prevent the USART from transmitting the data in the buffer and shift register,
and will make them available for new data. Any frame currently being transmitted will not be aborted.
Transmission of this frame will be completed.
The
USARTn_TXDOUBLEX, affect the transmission of the written frame. The following options are available:
• Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate
• Disable transmitter after transmission: If TXDISAT is set, the transmitter is disabled after the frame
• Enable receiver after transmission: If RXENAT is set, the receiver is enabled after the frame has
• Unblock receiver after transmission: If UBRXAT is set, the receiver is unblocked and RXBLOCK is
• Tristate transmitter after transmission: If TXTRIAT is set, TXTRI is set after the frame has been
a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g.
for framing of larger data packets. The line is driven high before the next frame is transmitted so the
next start condition can be identified correctly by the recipient. Continuous breaks lasting longer than
a USART frame are thus not supported by the USART. GPIO can be used for this.
has been fully transmitted.
been fully transmitted. It is enabled in time to detect a start-bit directly after the last stop-bit has been
transmitted.
cleared after the frame has been fully transmitted.
fully transmitted, tristating the transmitter output. Tristating of the output can also be performed
automatically by setting AUTOTRI.
TXDOUBLE,
TXDOUBLEX
transmission
control
TX buffer elem ent 1
TX buffer elem ent 0
Shift register
bits,
which
Peripheral Bus
can
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181
be
written
using
Write CTRL
Write CTRL
Write CTRL
USARTn_TXDATAX
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TXDATA,
TXDATAX
and