EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 325

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.4 Register Map
23.5 Register Description
23.5.1 ACMPn_CTRL - Control Register
31
30
29:28
27:24
23:18
17
16
15:11
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
Offset
0x000
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
FULLBIAS
Set this bit to 1 for full bias current in accordance with. Table 23.1 (p. 322) .
HALFBIAS
Set this bit to 1 to halve the bias current in accordance with. Table 23.1 (p. 322) .
Reserved
BIASPROG
These bits control the bias current level in accordance with. Table 23.1 (p. 322) .
Reserved
IFALL
Set this bit to 1 to set the EDGE interrupt flag on falling edges of comparator output.
IRISE
Set this bit to 1 to set the EDGE interrupt flag on rising edges of comparator output.
Reserved
Name
Value
0
1
Value
0
1
Name
ACMPn_CTRL
ACMPn_INPUTSEL
ACMPn_STATUS
ACMPn_IEN
ACMPn_IF
ACMPn_IFS
ACMPn_IFC
ACMPn_ROUTE
Mode
DISABLED
ENABLED
Mode
DISABLED
ENABLED
0
1
0x7
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
Access
Description
Interrupt flag is not set on falling edges
Interrupt flag is set on falling edges
Description
Interrupt flag is not set on rising edges
Interrupt flag is set on rising edges
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325
Bit Position
Type
RW
RW
R
RW
R
W1
W1
RW
Full Bias Current
Half Bias Current
Bias Configuration
Falling Edge Interrupt Sense
Rising Edge Interrupt Sense
Description
Description
Control Register
Input Selection Register
Status Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
I/O Routing Register
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