EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 19

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.3.1.1 Writing
5.3.1.2 Reading
2010-09-06 - d0001_Rev1.00
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized
into the Low Energy clock domain to maintain data consistency and predictable operation. Due to
synchronization, the write operation requires 3 positive edges of the clock of the Low Energy Peripheral
being accessed. Such registers are marked "Asynchronous" in their description header.
See Figure 5.2 (p. 19) for an overview of the writing operation.
After writing data to a register which value is to be synchronized into the Low Energy clock domain, a
corresponding busy flag in the <module_name>_SYNCBUSY register (e.g. RTC_SYNCBUSY) is set.
This flag is set as long as synchronization is in progress and is cleared upon completion.
Note
Figure 5.2. Write operation to Low Energy Peripherals
When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates
in the Low Energy clock domain or core clock domain. Registers which are updated/ maintained by the
Low Energy Peripheral are read directly from the Low Energy clock domain. Registers which originate in
the core clock domain, are read from the core clock domain. See Figure 5.3 (p. 20) for an overview
of the reading operation.
Note
Write[ 0:n]
Subsequent writes to the same register before the corresponding busy flag is cleared is not
supported. Write before the busy flag is cleared may result in undefined behavior.
In general the SYNCBUSY register only needs to be observed if there is a risk of multiple
write access to a register (which must be prevented). It is not required to wait until the
relevant flag in the SYNCBUSY register is cleared after writing a register. E.g can EM2 be
entered directly after writing a register.
Writing a register and then immediately reading the new value of the register may give the
impression that the write operation is complete. This may not be the case. Please refer
to the SYNCBUSY register for correct status of the write operation to the Low Energy
Peripheral.
Set 0
Set 1
Set n
Core Clock Dom ain
Core Clock
Syncbusy Register 0
Syncbusy Register 1
Syncbusy Register n
Register 0
Register 1
Register n
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.
.
.
.
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Clear 0
Clear 1
Clear n
Freeze
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19
Synchronization Done
Low Frequency Clock
Synchronizer 0
Synchronizer 1
Low Frequency Clock Dom ain
Synchronizer n
.
.
.
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Low Frequency Clock
Register 0 Sync
Register 1 Sync
Register n Sync
.
.
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