EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 48

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.2.3.6 Peripheral scatter-gather
2010-09-06 - d0001_Rev1.00
Task C
Primary, copy D
Task D
In peripheral scatter-gather mode the controller receives an initial request from a peripheral and then it
performs four DMA transfers using the primary data structure. It then immediately starts a DMA cycle
using the alternate data structure, without rearbitrating.
Note
After this cycle completes, the controller rearbitrates and if the controller receives a request from the
peripheral that has the highest priority then it performs another four DMA transfers using the primary
data structure. It then immediately starts a DMA cycle using the alternate data structure, without re-
arbitrating. The controller continues to switch from primary to alternate to primary… until either:
• the host processor configures the alternate data structure for a basic cycle
• it reads an invalid data structure.
The controller asserts dma_done[C] when the scatter-gather transaction completes using a basic cycle.
In scatter-gather mode, the controller uses the primary data structure to program the alternate data
structure. Table 8.5 (p. 48) lists the fields of the channel_cfg memory location for the primary data
structure, that you must program with constant values and those that can be user defined.
Table 8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode
Bit
Constant-value fields:
[31:30}
[29:28]
[27:26]
[25:24]
[17:14]
[2:0]
User defined values:
[23:21]
[20:18]
Note
Field
dst_inc
dst_size
src_inc
src_size
R_power
cycle_ctrl
dst_prot_ctrl
src_prot_ctrl
These are the only circumstances, where the controller does not enter the arbitration
process after completing a transfer using the primary data structure.
After the controller completes the N primary transfers it invalidates the primary data
structure by setting the cycle_ctrl field to b000.
Value
b10
b10
b10
b10
b0010
b110
-
-
8. The controller generates an auto-request for the channel and then arbitrates.
9. The controller performs task C. After it completes the task, it generates an
10. T he controller performs four DMA transfers. These transfers write the alternate
11. T he controller sets the cycle_ctrl bits of the primary data structure to b000, to
12. T he controller generates an auto-request for the channel and then arbitrates.
13. T he controller performs task D using an auto-request cycle.
14. T he controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters
auto-request for the channel and then arbitrates.
data structure for task D.
indicate that this data structure is now invalid.
the arbitration process.
Description
Configures the controller to use word increments for the address
Configures the controller to use word transfers
Configures the controller to use word increments for the address
Configures the controller to use word transfers
Configures the controller to perform four DMA transfers
Configures the controller to perform a peripheral scatter-gather DMA cycle
Configures the state of HPROT when the controller writes the destination data
Configures the state of HPROT when the controller reads the source data
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