EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 212

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.21 USARTn_IRCTRL - IrDA Control Register
31:13
12
11
10
9
8
7
6
5
4
3
2
1
0
31:8
7
6:4
Bit
Offset
0x050
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
CCF
Enable interrupt on collision check error detected.
SSM
Enable interrupt on slave-select in master mode.
MPAF
Enable interrupt on multi-processor address frame.
FERR
Enable interrupt on framing error.
PERR
Enable interrupt on parity error (asynchronous mode only).
TXUF
Enable interrupt on TX underflow.
TXOF
Enable interrupt on TX overflow.
RXUF
Enable interrupt on RX underflow.
RXOF
Enable interrupt on RX overflow.
RXFULL
Enable interrupt on RX Buffer full.
RXDATAV
Enable interrupt on RX data.
TXBL
Enable interrupt on TX buffer level.
TXC
Enable interrupt on TX complete.
Reserved
IRPRSEN
Enable the PRS channel selected by IRPRSSEL as input to IrDA module instead of TX.
IRPRSSEL
A PRS can be used as input to the pulse modulator instead of TX. This value selects the channel to use.
Name
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
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212
Bit Position
Collision Check Fail Interrupt Enable
Slave-Select In Master Mode Interrupt Enable
Multi-Processor Address Frame Interrupt Enable
Framing Error Interrupt Enable
Parity Error Interrupt Enable
TX Underflow Interrupt Enable
TX Overflow Interrupt Enable
RX Underflow Interrupt Enable
RX Overflow Interrupt Enable
RX Buffer Full Interrupt Enable
RX Data Valid Interrupt Enable
TX Buffer Level Interrupt Enable
TX Complete Interrupt Enable
IrDA PRS Channel Enable
IrDA PRS Channel Select
Description
Description
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