EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 34

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer
7.5.6 MSC_WDATA - Write Data Register
31:5
4
3
2
1
0
31:0
Bit
Offset
0x010
Reset
Access
Name
Bit
Offset
0x018
Reset
Access
Name
2010-09-06 - d0001_Rev1.00
Reserved
WRITETRIG
Start write of the first word written to MSC_WDATA, then add 4 to ADDR and write the next word if available within a 30us timeout.
When ADDR is incremented past the page boundary, ADDR is set to the base of the page.
WRITEONCE
Write the word in MSC_WDATA to ADDR. Flash access is returned to the AHB interface as soon as the write operation completes.
The WREN bit in the MSC_WRITECTRL register must be set in order to use this command.
WRITEEND
Write 1 to end write mode when using the WRITETRIG command.
ERASEPAGE
Erase any user defined page selected by the MSC_ADDRB register. The WREN bit in the MSC_WRITECTRL register must be set
in order to use this command.
LADDRIM
Load the internal write address register ADDR from the MSC_ADDRB register. The internal address register ADDR is incremented
automatically by 4 after each word is written. When ADDR is incremented past the page boundary, ADDR is set to the base of the page.
ADDRB
This register holds the page address for the erase or write operation. As a page is 512 bytes, bit [8:0] of this register are ignored for
erase commands. For write commands, bit [1:0] are ignored as writes are 32-bit wide only. This register is loaded into the internal
MSC_ADDR register when the LADDRIM field in MSC_CMD is set. The MSC_ADDR register is not readable.
Name
Name
0
0
0
0
0
0x00000000
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
W1
W1
W1
W1
W1
RW
Access
Access
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Bit Position
Bit Position
34
Word Write Sequence Trigger
Word Write-Once Trigger
End Write Mode
Erase Page
Load MSC_ADDRB into ADDR
Page Erase or Write Address Buffer
Description
Description
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