EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 107

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.5.12 CMU_STATUS - Status Register
1:0
31:15
14
13
12
11
10
9
8
7
6
5
4
Bit
Offset
0x02C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
LFA
Selects the clock source for LFACLK.
Reserved
CALBSY
Calibration is on-going.
LFXOSEL
LFXO is selected as HFCLK clock source.
LFRCOSEL
LFRCO is selected as HFCLK clock source.
HFXOSEL
HFXO is selected as HFCLK clock source.
HFRCOSEL
HFRCO is selected as HFCLK clock source.
LFXORDY
LFXO is enabled and start-up time has exceeded.
LFXOENS
LFXO is enabled.
LFRCORDY
LFRCO is enabled and start-up time has exceeded.
LFRCOENS
LFRCO is enabled.
AUXHFRCORDY
AUXHFRCO is enabled and start-up time has exceeded.
AUXHFRCOENS
AUXHFRCO is enabled.
Name
Name
Value
1
2
3
Value
0
1
2
3
Mode
LFRCO
LFXO
HFCORECLKLEDIV2
Mode
DISABLED
LFRCO
LFXO
HFCORECLKLEDIV2
0x1
0
0
0
0
1
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
R
R
R
R
R
R
R
R
R
R
R
Access
Access
Description
LFRCO selected as LFBCLK
LFXO selected as LFBCLK
HFCORECLK
Description
LFACLK is disabled
LFRCO selected as LFACLK
LFXO selected as LFACLK
HFCORECLK
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107
Bit Position
Clock Select for LFA
Calibration Busy
LFXO Selected
LFRCO Selected
HFXO Selected
HFRCO Selected
LFXO Ready
LFXO Enable Status
LFRCO Ready
LFRCO Enable Status
AUXHFRCO Ready
AUXHFRCO Enable Status
Description
Description
LE
LE
divided by two is selected as LFBCLK
divided by two is selected as LFACLK
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