EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 395

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

28.3.4 Output to PRS
28.3.5 Synchronization
2010-09-06 - d0001_Rev1.00
All pins with the same pin number (n) are grouped together to form one PRS producer output, giving
a total of 16 outputs to the PRS. The port on which the output n should be taken is selected by the
EXTIPSELn[3:0] bits in the GPIO_EXTIPSELL or the GPIO_EXTIPSELH registers.
To avoid metastability in synchronous logic connected to the pins, all inputs are synchronized with
double flip-flops. The flip-flops for the input data run on the HFCORECLK. Consequently, when a
pin changes state, the change will have propagated to GPIO_Px_DIN after 2 positive HFCORECLK
edges, or maximum 2 HFCORECLK cycles. Synchronization (also running on the HFCORECLK) is also
added for interrupt input. The input to the PRS generation is also synchronized, but these flip-flops
run on the HFPERCLK. To save power when the external interrupts or PRS generation is not used,
the synchronization flip-flops for these can be turned off by clearing the INTSENSE or PRSSENSE,
respectively, in GPIO_INSENSE register.
Note
To use the GPIO, the GPIO clock must first be enabled in CMU_HFPERCLKEN0. Setting
this bit enables the HFCORECLK and the HFPERCLK for the GPIO. HFCORECLK is used
for updating registers, while HFPERCLK is only used to synchronize PRS and interrupts.
The PRS and interrupt synchronization can also be disabled through GPIO_INSENSE, if
these are not used.
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