EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 42

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.2.3 DMA cycle types
2010-09-06 - d0001_Rev1.00
After a DMA transfer completes, the controller polls all the DMA channels that are available. Figure 8.2 (p.
42) shows the process it uses to determine which DMA transfer to perform next.
Figure 8.2. Polling flowchart
The cycle_ctrl bits control how the controller performs a DMA cycle. You can set the cycle_ctrl bits as
Table 8.3 (p. 42) lists.
Table 8.3. DMA cycle types
Channel
number
6
7
cycle_ctrl
b000
b001
3
4
5
1
2
Select channel that has
using a high priority-
num ber and is set to
the lowest channel
channel requests
high priority-level
Start polling
a channel
request ?
Is there
Are any
level ?
Priority level
setting
Default
Default
Default
Default
Default
Default
Default
Yes
Yes
Description
Channel control data structure is invalid
Basic DMA transfer
Start DMA transfer
N
Descending order of
channel priority
-
-
-
-
-
-
Lowest-priority DMA channel
o
No
Select channel that has
the lowest channel
num ber
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