EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 317

MCU 32BIT 64KB FLASH 32-QFN

EFM32G200F64

Manufacturer Part Number
EFM32G200F64
Description
MCU 32BIT 64KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F64

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Quantity
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Part Number:
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22.5.9 PCNTn_IFC - Interrupt Flag Clear Register
22.5.10 PCNTn_IEN - Interrupt Enable Register
31:3
2
1
0
31:3
2
1
0
31:3
2
1
Bit
Offset
0x020
Reset
Access
Name
Bit
Offset
0x024
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
DIRCNG
Write to 1 to set the direction change interrupt flag
OF
Write to 1 to set the overflow interrupt flag
UF
Write to 1 to set the underflow interrupt flag
Reserved
DIRCNG
Write to 1 to clear the direction change detect interrupt flag
OF
Write to 1 to clear the overflow interrupt flag
UF
Write to 1 to clear the underflow interrupt flag
Reserved
DIRCNG
Enable the direction change detect interrupt.
OF
Name
Name
Name
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
RW
RW
Access
Access
Access
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317
Bit Position
Bit Position
Direction Change Detect Interrupt Set
Overflow Interrupt Set
Underflow interrupt set
Direction Change Detect Interrupt Clear
Overflow Interrupt Clear
Underflow Interrupt Clear
Direction Change Detect Interrupt Enable
Overflow Interrupt Enable
Description
Description
Description
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