EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 247

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.3.1.6.1 X2 Decoding Mode
2010-09-06 - d0001_Rev1.00
Figure 19.6. TIMER Quadrature Encoded Inputs
In the Timer these inputs are tapped from the Compare/Capture channel 0 (Channel A) and 1 (Channel
B) inputs before edge detection. The Timer/Counter then increments or decrements the counter, based
on the phase relation between the two inputs. The Quadrature Decoder Mode supports two channels,
but if a third channel (Z-terminal) is available, this can be connected to an external interrupt and trigger
a counter reset from the interrupt service routine. By connecting a periodic signal from another timer as
input capture on Compare/Capture Channel 2, it is also possible to calculate speed and acceleration.
Figure 19.7. TIMER Quadrature Decoder Configuration
The Quadrature Decoder can be set in either X2 or X4 mode, which is configured in the QDM bit in
TIMERn_CTRL. See Figure 19.7 (p. 247)
In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see
Table 19.1 (p. 248) and Figure 19.8 (p. 248) .
Com pa r e /Ca pt u r e ch a n n e l 0
(Controlled by TIMERn_CC0_CTRL)
Com pa r e /Ca pt u r e ch a n n e l 1
(Controlled by TIMERn_CC1_CTRL)
Channel A
Channel B
Channel A
Channel B
PRS channels
PRS channels
TIMn_CC0
TIMn_CC1
PRSSEL
PRSSEL
Backward rotation (Channel B leads Channel A)
90
90
Forward rotation (Channel A leads Channel B)
°
°
INSEL
INSEL
Filter
Filter
FILT
FILT
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247
ICEDGE
ICEDGE
Capture 0
Capture 1
Input
Input
Cou n t e r
(Controlled by TIMERn_CTRL)
Ch A
Ch B
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QDM
Qu a dr a t u r e
De code r
Inc
Dec
MODE
Cou n t e r