EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 157

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-09-06 - d0001_Rev1.00
After a START or repeated START condition, the bus master will transmit an address along with an R/
W bit. If there is no room in the receive shift register for the address, the bus will be held by the slave
until room is available in the shift register. Transmission then continues and the address is loaded into
the shift register. If this address does not pass address recognition, it is automatically NACK’ed by the
slave, and the slave goes to an idle state. The address byte is in this case discarded, making the shift
register ready for a new address. It is not loaded into the receive buffer.
If the address was accepted and the R/W bit was set (R), indicating that the master wishes to read from
the slave, the slave now goes into the slave transmitter mode. Software interaction is now required to
decide whether the slave wants to acknowledge the request or not. The accepted address byte is loaded
into the receive buffer like a regular data byte. If no valid interaction is pending, the bus is held until the
slave responds with a command. The slave can reject the request with a single NACK command.
The slave will in that case go to an idle state, and wait for the next start condition. To continue the
transmission, the slave must make sure data is loaded into the transmit buffer and send an ACK. The
loaded data will then be transmitted to the master, and an ACK or NACK will be received from the master.
Data transmission can also continue after a NACK if a CONT command is issued along with the NACK.
This is not standard I
If the master responds with an ACK, it may expect another byte of data, and data should be made
available in the transmit buffer. If data is not available, the bus is held until data is available.
If the response is a NACK however, this is an indication of that the master has received enough bytes
and wishes to end the transmission. The slave now automatically goes idle, unless CONT in I2Cn_CMD
is set and data is available for transmission. The latter is not standard I
The master ends the transmission by sending a STOP or a repeated START. The SSTOP interrupt
flag in I2Cn_IF is set when the master transmits a STOP condition. If the transmission is ended with a
repeated START, then the SSTOP interrupt flag is not set.
Note
If arbitration is lost at any time during transmission, the ARBLOST interrupt flag in I2Cn_IF is set, the
bus is released and the slave goes idle.
See Table 15.8 (p. 158) for more information.
The SSTOP interrupt flag in I2Cn_IF will be set regardless of whether the slave is
participating in the transmission or not, as long as SLAVE in I2Cn_CTRL is set and a STOP
condition is detected
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