EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 314

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.5.2 PCNTn_CMD - Command Register (Async Reg)
22.5.3 PCNTn_STATUS - Status Register
2
1:0
31:2
1
0
31:1
Bit
Offset
0x004
Reset
Access
Name
Bit
Offset
0x008
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
CNTDIR
The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EXTCLKQUAD mode
as the direction is automatically detected.
MODE
Selects the mode of operation. The corresponding clock source must be selected from the CMU.
Reserved
LTOPBIM
This bit has no effect since TOPB is not buffered and it is loaded directly into TOP. For EFM32G revisions A and B: Load PCNTn_TOPB
into PCNTn_TOP. Please see the device datasheet for a description on how to extract the chip revision.
LCNTIM
Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle.
Reserved
Name
Name
Name
Value
0
1
Value
0
1
2
3
Mode
UP
DOWN
Mode
DISABLE
OVSSINGLE
EXTCLKSINGLE
EXTCLKQUAD
0
0x0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
W1
W1
Access
Access
Access
Description
Up counter mode
Down counter mode
Description
The module is disabled
Single input LFACLK oversampling mode (available in EM0-EM2)
Externally clocked single input counter mode (available in EM0-EM3)
Externally clocked quadrature decoder mode (available in EM0-EM3)
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314
Bit Position
Bit Position
Non-Quadrature Mode Counter Direction Control
Mode Select
Load TOPB Immediately
Load CNT Immediately
Description
Description
Description
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