EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 447

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

30.3 Revision 0.83
30.4 Revision 0.82
30.5 Revision 0.81
2010-09-06 - d0001_Rev1.00
Split DTOGEN in TIMER0_DTOGEN into single bits.
Split DTFSEN in TIMER0_DTFC into single bits.
Split DTFS in TIMER0_DTFAULT into single bits.
Split DTFSC in TIMER0_DTFAULTC into single bits.
DTPRSFSEL0 in TIMER0_DTFC renamed to DTPRS0FSEL.
DTPRSFSEL1 in TIMER0_DTFC renamed to DTPRS1FSEL.
January 25th, 2010
ENERGYMODE bitfield in ADCn_CTRL, renamed to WARMUPMODE.
Updated enumeration for SCANMASK in ADCn_SCANCTRL.
Updated enumeration for SINGLESEL in ADCn_SINGLECTRL.
Updated enumeration for SCANDATASRC in ADCn_STATUS.
Specified default drive strength for GPIO pins in Section 28.3.1 (p. 391) .
Extracted I
Moved specification of resistance values of CSRESEL in ACMPn_CTRL to datasheets.
Corrected DAC clock prescaling equation (Equation 26.1 (p. 364) )
November 20th, 2009
Description of LFXOSEL and LFRCOSEL bits of CMU_STATUS register corrected.
Updated description of EM4 sequence in Table 10.2 (p. 85) .
Updated documentation of WORDTIMEOUT and WDATAREADY in MSC_STATUS.
November 13th, 2009
Note added to Section 7.3.6 (p. 31) .
Note added to Section 7.3.6 (p. 31) .
Internal reference added to Section 5.6 (p. 21) .
DMA_CHx_CTRL register description updated.
Reference to synchronous pin interrupts removed from Chapter 10 (p. 81) .
ACMP wakeup triggering updated in Chapter 10 (p. 81) .
Internal reference added to note in Section 11.3.1.2 (p. 93) .
Figure 11.4 (p. 96) and Figure 11.5 (p. 97) added.
2
C Slave State Machine into separate section (Section 15.3.9 (p. 155) )
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