EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 120

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.3.1 Clock Source
12.3.2 Debug Functionality
12.3.3 Energy Mode Handling
12.3.4 Register access
2010-09-06 - d0001_Rev1.00
Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL.
The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be
written to prevent accidental disabling of the selected clocks. Also, setting this bit will automatically start
the selected oscillator source when the watchdog is enabled. The PERSEL field in WDOG_CTRL is used
to divide the selected watchdog clock, and the timeout for the watchdog timer can be calculated like this:
WDOG Timeout Equation
where f is the frequency of the selected clock.
It is recommended to clear the watchdog first, if PERSEL is changed while the watchdog is enabled.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to
the module clock.
The watchdog timer can either keep running or be frozen when the device enters debug mode. This
configuration is done through the DEBUGRUN bit in WDOG_CTRL. When the device leaves debug
mode, the watchdog will continue counting where it left off.
The watchdog timer can be configured to either keep on running or freeze when entering EM2 or EM3.
The configuration is done individually for each energy mode in the EM2RUN and EM3RUN bits in
WDOG_CTRL. When the watchdog has been frozen and is re-entering an energy mode where it is
running, the watchdog timer will continue counting where it left off. For the watchdog there is no difference
between EM0 and EM1. The watchdog does not run in EM4, and if writing to the EM4BLOCK bit in
WDOG_CTRL, the CPU is prevented from entering EM4.
Note
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to
the HFCORECLK, special considerations must be taken when accessing registers. Please refer to
Section 5.3 (p. 18) for a description on how to perform register accesses to Low Energy Peripherals.
note that clearing the EN bit in WDOG_CTRL will reset the WDOG module, which will halt any ongoing
register synchronization.
Writing the SWOSCBLOCK bit will effectively prevent the CPU from entering EM3.
T
TIMEOUT
= (2
3+PERSEL
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+ 1)/f
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(12.1)