EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 370

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.5.2 DACn_STATUS - Status Register
26.5.3 DACn_CH0CTRL - Channel 0 Control Register
31:2
1
0
31:7
6:4
3
2
Bit
Offset
0x004
Reset
Access
Name
Bit
Offset
0x008
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
CH1DV
This bit is set high when CH1DATA is written and is set low when CH1DATA is used in conversion.
CH0DV
This bit is set high when CH0DATA is written and is set low when CH0DATA is used in conversion.
Reserved
PRSSEL
Select Channel 0 PRS input channel.
Reserved
PRSEN
Name
Name
Name
Value
0
1
Value
0
1
2
3
4
5
6
7
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
Description
Single ended output
Differential output
0
0
0x0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
RW
RW
Access
Access
Access
Description
PRS ch 0 triggers channel 0 conversion.
PRS ch 1 triggers channel 0 conversion.
PRS ch 2 triggers channel 0 conversion.
PRS ch 3 triggers channel 0 conversion.
PRS ch 4 triggers channel 0 conversion.
PRS ch 5 triggers channel 0 conversion.
PRS ch 6 triggers channel 0 conversion.
PRS ch 7 triggers channel 0 conversion.
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370
Bit Position
Bit Position
Channel 1 Data Valid
Channel 0 Data Valid
Channel 0 PRS Trigger Select
Channel 0 PRS Trigger Enable
Description
Description
Description
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