EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 273

MCU 32BIT 64KB FLASH 32-QFN

EFM32G200F64

Manufacturer Part Number
EFM32G200F64
Description
MCU 32BIT 64KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F64

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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19.5.19 TIMERn_DTOGEN - DTI Output Generation Enable Register
15:11
10:8
7:3
2:0
31:6
5
4
3
2
Bit
Offset
0x07C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
DTPRS1FSEL
Select PRS channel for fault source 1.
Reserved
DTPRS0FSEL
Select PRS channel for fault source 0.
Reserved
DTOGCDTI2EN
This bit enables/disables output generation for the CDTI2 output from the DTI.
DTOGCDTI1EN
This bit enables/disables output generation for the CDTI1 output from the DTI.
DTOGCDTI0EN
This bit enables/disables output generation for the CDTI0 output from the DTI.
DTOGCC2EN
This bit enables/disables output generation for the CC2 output from the DTI.
Name
Name
Value
3
Value
0
1
2
3
4
5
6
7
Value
0
1
2
3
4
5
6
7
Mode
TRISTATE
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
0x0
0x0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Access
Description
Tristate outputs
Description
PRS Channel 0 selected as fault source 1
PRS Channel 1 selected as fault source 1
PRS Channel 2 selected as fault source 1
PRS Channel 3 selected as fault source 1
PRS Channel 4 selected as fault source 1
PRS Channel 5 selected as fault source 1
PRS Channel 6 selected as fault source 1
PRS Channel 7 selected as fault source 1
Description
PRS Channel 0 selected as fault source 0
PRS Channel 1 selected as fault source 0
PRS Channel 2 selected as fault source 0
PRS Channel 3 selected as fault source 0
PRS Channel 4 selected as fault source 0
PRS Channel 5 selected as fault source 0
PRS Channel 6 selected as fault source 0
PRS Channel 7 selected as fault source 0
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Bit Position
DTI PRS Fault Source 1 Select
DTI PRS Fault Source 0 Select
DTI CDTI2 Output Generation Enable
DTI CDTI1 Output Generation Enable
DTI CDTI0 Output Generation Enable
DTI CC2 Output Generation Enable
Description
Description
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