EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 444

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

30 Revision History
30.1 Revision 1.00
2010-09-06 - d0001_Rev1.00
September 6th, 2010
Parity bits not available for USART synchronous mode.
Corrected Scaled VDD equation in Section 23.3.4 (p. 323) .
DACOUT0 and DACOUT1 in ADCn_SINGLECTRL renamed to DAC0OUT0 and DAC0OUT1.
CH4 in ADCn_SINGLECTRL under DIFF = 1 renamed to DIFF0.
Changed note about minimum acquisition time when sampling V
Added information about new individual LCD pin disable feature.
Switched LPFMODE DECAP and RCFILT in ADCn_CTRL register description.
Added EBI Regions and Peripheral Bit Band Alias to System Address Space in Figure 5.1 (p. 14) .
Changed VCMP_INPUTCTRL to VCMP_INPUTSEL in Section 24.3.4 (p. 333) , it now complies with
register description.
Corrected conversion time numbers in Section 25.3.2 (p. 341) .
Changed ENERGYMODE to WARMUPMODE in Section 25.3.3 (p. 342) .
Added Result Resolution column in Table 25.3 (p. 346) .
Changed ADC calibration routines in Section 25.3.10 (p. 347) .
Added table with ADC calibration register effect (Table 25.5 (p. 348) ).
Improved ADC Input Filter description and added Figure 25.3 (p. 343) .
Added minimum supply voltage restrictions when using the 2.5 V and 5 V bandgap references.
Added note about FULLBIAS and hysteresis level in Section 23.3.2 (p. 322) .
Removed V
Improved register description on SCANGAIN, SCANOFFSET, SINGLEGAIN and SINGLEOFFSET
fields in ADCn_CAL.
HPROT[3] and HPROT[2] were removed because there is no cache and bufferable implementation in
the system.
CHPROT is not only 1 bit for the above reason.
DMA_CONFIG register is W and not RW.
On the PCNT module, the user does not have to issue LTOPBIM command to load TOPB to TOP so
this bit has no effect.
Corrected AES 128/256 encryption/decryption duration to 54/75 cycles.
Corrected description of AES byte order for data and key.
ss
as possible negative input selection for the analog comparator in Figure 23.1 (p. 321) .
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dd
/3 in Section 25.3.4 (p. 342) .
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