EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 50

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.2.4 Error signaling
8.4.3 Channel control data structure
2010-09-06 - d0001_Rev1.00
Primary, copy A
Task A
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy B
Task B
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy C
Task C
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy D
Task D
If the controller detects an ERROR response on the AHB-Lite master interface, it:
• disables the channel that corresponds to the ERROR
• sets dma_err HIGH.
After the host processor detects that dma_err is HIGH, it must check which channel was active when
the ERROR occurred. It can do this by:
1. Reading the DMA_CHENS register to create a list of disabled channels.
When a channel asserts dma_done[ ] then the controller disables the channel. The program running
on the host processor must always keep a record of which channels have recently asserted their
dma_done[ ] outputs.
2. It must compare the disabled channels list from step 1 (p. 50) , with the record of the channels that
You must provide an area of system memory to contain the channel control data structure. This system
memory must:
have recently set their dma_done[ ] outputs. The channel with no record of dma_done[C] being
set is the channel that the ERROR occurred on.
1. After receiving a request, the controller performs four DMA transfers. These
2. The controller performs task A.
3. After the controller completes the task it enters the arbitration process.
4. The controller performs four DMA transfers. These transfers write the alternate
5. The controller performs task B. To enable the controller to complete the task,
6. After the controller completes the task it enters the arbitration process.
7. The controller performs four DMA transfers. These transfers write the alternate
8. The controller performs task C.
9. After the controller completes the task it enters the arbitration process.
10. T he controller performs four DMA transfers. These transfers write the alternate
11. T he controller sets the cycle_ctrl bits of the primary data structure to b000, to
12. T he controller performs task D using a basic cycle.
13. T he controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters
transfers write the alternate data structure for task A.
data structure for task B.
the peripheral must issue a further three requests.
data structure for task C.
data structure for task D.
indicate that this data structure is now invalid.
the arbitration process.
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