EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 381

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

27.4 Register Map
27.5 Register Description
27.5.1 AES_CTRL - Control Register
31:6
5
4
3
2
1
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
Offset
0x000
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
Reserved
XORSTART
Set this bit to start encryption/decryption when DATA3 is written through AES_XORDATA.
DATASTART
Set this bit to start encryption/decryption when DATA3 is written through AES_DATA.
Reserved
KEYBUFEN
Enable/disable key buffer in AES-128 mode.
AES256
Select AES-128 or AES-256 mode.
Name
Name
AES_CTRL
AES_CMD
AES_STATUS
AES_IEN
AES_IF
AES_IFS
AES_IFC
AES_DATA
AES_XORDATA
AES_KEYLA
AES_KEYLB
AES_KEYLC
AES_KEYLD
AES_KEYHA
AES_KEYHB
AES_KEYHC
AES_KEYHD
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
Access
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381
Bit Position
Type
RW
W1
R
RW
R
W1
W1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
AES_XORDATA Write Start
AES_DATA Write Start
Key Buffer Enable
AES-256 Mode
Description
Description
Control Register
Command Register
Status Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
DATA Register
XORDATA Register
KEY Low Register
KEY Low Register
KEY Low Register
KEY Low Register
KEY High Register
KEY High Register
KEY High Register
KEY High Register
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