EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 79

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.4 Register Map
9.5 Register Description
9.5.1 RMU_CTRL - Control Register
9.5.2 RMU_RSTCAUSE - Reset Cause Register
31:1
0
31:7
6
5
4
Offset
0x000
0x004
0x008
Offset
0x000
Reset
Access
Name
Bit
Offset
0x004
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
Reserved
LOCKUPRDIS
Set this bit to disable the LOCKUP signal(from the Cortex-M3) from resetting the device.
Reserved
SYSREQRST
Set if a system request reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 76) for details on how
to interpret this bit.
LOCKUPRST
Set if a LOCKUP reset has been requested. Must be cleared by software. Please see Table 9.1 (p. 76) for details on how to interpret
this bit.
WDOGRST
Set if a watchdog reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 76) for details on how to interpret
this bit.
Name
Name
Name
RMU_CTRL
RMU_RSTCAUSE
RMU_CMD
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
R
R
R
Access
Access
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Bit Position
Bit Position
79
Type
RW
R
W1
Lockup Reset Disable
System Request Reset
LOCKUP Reset
Watchdog Reset
Description
Description
Description
Control Register
Reset Cause Register
Command Register
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