EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 373

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.5.7 DACn_IFS - Interrupt Flag Set Register
26.5.8 DACn_IFC - Interrupt Flag Clear Register
31:6
5
4
3:2
1
0
31:6
5
4
3:2
1
0
Bit
Offset
0x018
Reset
Access
Name
Bit
Offset
0x01C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Indicates channel 0 conversion complete.
Reserved
CH1UF
Write to 1 to set channel 1 Data Underflow interrupt flag.
CH0UF
Write to 1 to set channel 0 Data Underflow interrupt flag.
Reserved
CH1
Write to 1 to set channel 1 conversion complete interrupt flag.
CH0
Write to 1 to set channel 0 conversion complete interrupt flag.
Reserved
CH1UF
Write to 1 to clear channel 1 data underflow interrupt flag.
CH0UF
Write to 1 to clear channel 0 data underflow interrupt flag.
Reserved
CH1
Write to 1 to clear channel 1 conversion complete interrupt flag.
CH0
Name
Name
Name
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
W1
W1
Access
Access
Access
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373
Bit Position
Bit Position
Channel 1 Data Underflow Interrupt Flag Set
Channel 0 Data Underflow Interrupt Flag Set
Channel 1 Conversion Complete Interrupt Flag Set
Channel 0 Conversion Complete Interrupt Flag Set
Channel 1 Data Underflow Interrupt Flag Clear
Channel 0 Data Underflow Interrupt Flag Clear
Channel 1 Conversion Complete Interrupt Flag Clear
Channel 0 Conversion Complete Interrupt Flag Clear
Description
Description
Description
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