EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 366

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.3.6 Interrupts and PRS Output
26.3.7 DMA Request
26.3.8 Analog Output
2010-09-06 - d0001_Rev1.00
The output driver is controlled by the PRS line selected by PRSSEL in DACn_CH1CTRL, the output is
enabled when the PRS line goes high. The sine wave keeps running even if the output is disabled. Each
period, starting at 0 degrees, is made up of 16 samples and the frequency is given by Equation 26.4 (p.
366) :
DAC Sine Generation
The SINE wave will be output on channel 0. If DIFF is set in DACn_CTRL, the sine wave will be output
on both channels (if enabled), but inverted (see Figure 26.3 (p. 366) ). Note that when OUTENPRS
in DACn_CTRL is set, the sine output will be reset to 0 degrees when the PRS line selected by
CH1PRSSEL is low.
Figure 26.3. DAC Sine Mode
Both DAC channels have separate interrupt flags (in DACn_IF) indicating that a conversion has finished
on the channel and that new data can be written to the data registers. Setting one of these flags will result
in a DAC interrupt if the corresponding interrupt enable bit is set in DACn_IEN. All generated interrupts
from the DAC will activate the same interrupt vector when enabled.
The DAC has two PRS outputs which will carry a one cycle (HFPERCLK) high pulse when the
corresponding channel has finished a conversion.
The DAC sends out a DMA request when a conversion on a channel is complete. This request is cleared
when the corresponding channel’s data register is written.
Each DAC channel has its own output pin (DACn_OUT0 and DACn_OUT1) in addition to an internal
loopback to the ADC. These outputs can be enabled and disabled individually in the OUTPUTSEL field
in DACn_CTRL register. The DAC outputs can also be directed to the ADC, which is also configurable
in the OUTPUTSEL field in DACn_CTRL.
The DAC outputs are tristated when the channels are not enabled. By setting the OUTENPRS
bit in DACn_CTRL, the outputs are also tristated when the PRS line selected by CH1PRSSEL in
DACn_CH1CTRL is low. When the PRS signal is high, the outputs are enabled as normal.
DACn_OUT1
DACn_OUT0
CH0 PRS
CH1 PRS
f
sine
= f
HFPERCLK
Hi-Z
Hi-Z
/ 32 x (PRESC + 1)
...the world's most energy friendly microcontrollers
366
www.energymicro.com
Vref
Vref/2
0
Vref
Vref/2
0
(26.4)