EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 333

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

24.3.3 Hysteresis
24.3.4 Input Selection
24.3.5 Interrupts and PRS Output
2010-09-06 - d0001_Rev1.00
In the voltage supply comparator, hysteresis can be enabled by setting HYSTEN in VCMP_CTRL. When
HYSTEN is set, the digital output will not toggle until the positive input voltage is at least 20mV above
or below the negative input voltage. This feature can be used to filter out uninteresting input fluctuations
around zero and only show changes that are big enough to breach the hysteresis threshold.
Figure 24.2. VCMP 20 mV Hysteresis Enabled
The positive comparator input is always connected to the scaled power supply input. The negative
comparator input is connected to the internal 1.25 V bandgap reference. The V
configured by setting the TRIGLEVEL field in VCMP_CTRL according to the following formula:
VCMP V
A low power reference mode can be enabled by setting the LPREF bit in VCMP_INPUTSEL. In this mode,
the power consumption in the reference buffer (V
The VCMP includes an edge triggered interrupt flag (EDGE in VCMP_IF). If either IRISE and/or IFALL in
VCMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator
BIAS
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
DD
Trigger Level
VCMPOUT without hysteresis
VCMPOUT with hysteresis
V
DD Trigger Level
In
In
NEG
NEG
+ 20m V
-20m V
In
HALFBIAS=0
1.2
1.4
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
NEG
= 1.667V + 0.034V × TRIGLEVEL
In
POS
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333
DD
and bandgap) is lowered at the cost of accuracy.
Bias Current (µA)
HALFBIAS=1
0.6
0.7
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
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DD
Tim e
trigger level can be
(24.1)