EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 224

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.3.5.4 Parity Error
18.3.5.5 Framing Error and Break Detection
18.3.5.6 Programmable Start Frame
2010-09-06 - d0001_Rev1.00
where n is the bit-index.
Since samples are only done on the positive edges of the 32.768 kHz clock, the actual samples are
performed on the closest positive edge, i.e. the edge given by the following equation:
LEUART Actual Sampling Point
The sampling location will thus have jitter according to difference between S
found at n=0, then follows the data bits, any parity bit, and the stop bits.
If the value of the start-bit is found to be high, then the start-bit is discarded, and the receiver waits for
a new start-bit.
When the parity bit is enabled, a parity check is automatically performed on incoming frames. When
a parity error is detected in a frame, the data parity error bit PERR in the frame is set, as well as the
interrupt flag PERR. Frames with parity errors are loaded into the receive buffer like regular frames.
PERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX
register.
A framing error is the result of a received frame where the stop bit was sampled to a value of 0. This
can be the result of noise and baud rate errors, but can also be the result of a break generated by the
transmitter on purpose.
When a framing error is detected, the framing error bit FERR in the received frame is set. The interrupt
flag FERR in LEUARTn_IF is also set. Frames with framing errors are loaded into the receive buffer
like regular frames.
FERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX
or LEUARTn_RXDATAXP registers.
The LEUART can be configured to start receiving data when a special start frame is detected on the input.
This can be useful when operating in low energy modes, allowing other devices to gain the attention of
the LEUART by transmitting a given frame.
When SFUBRX in LEUARTn_CTRL is set, an incoming frame matching the frame defined in
LEUARTn_STARTFRAME will result in RXBLOCK in LEUARTn_STATUS being cleared. This can be
used to enable reception when a specified start frame is detected. If the receiver is enabled and blocked,
i.e. RXENS and RXBLOCK in LEUARTn_STATUS are set, the receiver will receive all incoming frames,
but unless an incoming frame is a start frame it will be discarded and not loaded into the receive buffer.
When a start frame is detected, the block is cleared, and frames received from that point, including the
start frame, are loaded into the receive buffer.
An incoming start frame results in the STARTF interrupt flag in LEUARTn_IF being set, regardless of
the value of SFUBRX in LEUARTn_CTRL. This allows an interrupt to be made when the start frame
is detected.
S(n) = floor(n x (1 + LEUARTn_CLKDIV/256) + LEUARTn_CLKDIV/512)
S
opt
(n) = n (1 + LEUARTn_CLKDIV/256) + CLKDIV/512
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opt
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and S. The start-bit is
(18.3)
(18.4)