EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 18

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.2.3.2 Access Performance
5.3 Access to Low Energy Peripherals (Asynchronous Registers)
5.3.1 Introduction
2010-09-06 - d0001_Rev1.00
The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth
of 4x a single AHB interface.
The Bus Matrix accepts new transfers to be initiated by each master in each cycle without inserting any
wait-states. However, the slaves may insert wait-states depending on their internal throughput and the
clock frequency.
The Cortex-M3 and the DMA Controller, and the peripherals (not peripherals in the low frequency clock
domain) run on clocks which can be prescaled separately. When accessing a peripheral which runs on
a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition
to master arbitration, is given by:
Memory Wait Cycles with Clock Equal or Faster than the HFCORECLK
where N
When accessing a peripheral which runs on a slower clock than the HFCORECLK, wait cycles are
introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per
access, in addition to master arbitration, is given by:
Memory Wait Cycles with Clock Slower than the CPU
where N
Clocks and prescaling are described in more detail in Chapter 11 (p. 90) .
The Low Energy Peripherals are capable of running when the high frequency oscillator and core system
is powered off, i.e. in energy modes EM2 and in some cases also EM3. This enables the peripherals to
perform tasks while the system energy consumption is minimal.
The Low Energy Peripherals are:
• Liquid Crystal Display driver - LCD
• Low Energy Timer - LETIMER
• Low Energy UART - LEUART
• Pulse Counter - PCNT
• Real Time Counter - RTC
• Watchdog - WDOG
All Low Energy Peripherals are memory mapped, with standardized data synchronization support.
Because the Low Energy Peripherals are running on clocks asynchronous to the core clock, there are
some constraints on how register accesses are performed, as described in the following sections. The
constraints are however standardized across all Low Energy Peripherals.
slave cycles
slave cycles
is the wait cycles introduced by the slave.
is the wait cycles introduced by the slave.
N
cycles
= (2 + N
N
cycles
slave cycles
= 2 + N
) x f
...the world's most energy friendly microcontrollers
slave cycles
18
HFCORECLK
/f
HFPERCLK
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(5.3)
(5.4)