EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 113

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0
(Async Reg)
11.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0
(Async Reg)
31:1
0
31:3
2
1
0
31:2
1
0
Bit
Offset
0x058
Reset
Access
Name
Bit
Offset
0x060
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
REGFREEZE
When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to update several
registers simultaneously.
Reserved
LCD
Set to enable the clock for LCD.
LETIMER0
Set to enable the clock for LETIMER0.
RTC
Set to enable the clock for RTC.
Reserved
LEUART1
Set to enable the clock for LEUART1.
LEUART0
Set to enable the clock for LEUART0.
Name
Name
Name
Value
0
1
Mode
UPDATE
FREEZE
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Access
Access
Description
Each write access to a Low Frequency clock control register is updated into the Low
Frequency domain as soon as possible.
The LE Clock Control registers are not updated with the new written value.
...the world's most energy friendly microcontrollers
113
Bit Position
Bit Position
Register Update Freeze
Liquid Crystal Display Controller Clock Enable
Low Energy Timer 0 Clock Enable
Real-Time Counter Clock Enable
Low Energy UART 1 Clock Enable
Low Energy UART 0 Clock Enable
Description
Description
Description
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