EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 318

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.5.11 PCNTn_ROUTE - I/O Routing Register
22.5.12 PCNTn_FREEZE - Freeze Register
0
31:10
9:8
7:0
31:1
0
Bit
Offset
0x028
Reset
Access
Name
Bit
Offset
0x02C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Enable the overflow interrupt
UF
Enable the underflow interrupt
Reserved
LOCATION
Defines the location of the PCNT input pins. E.g. PCNTn_S0#0, #1 or #2.
Reserved
Reserved
REGFREEZE
When set, the update of the PCNT clock domain is postponed until this bit is cleared. Use this bit to update several registers
simultaneously.
Name
Name
Name
Value
0
1
2
Value
0
1
Mode
LOC0
LOC1
LOC2
Mode
UPDATE
FREEZE
0
0x0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
Access
Access
Access
Description
Select location 0
Select location 1
Select location 2
Description
Each write access to a PCNT register is updated into the Low Frequency domain as
soon as possible.
The PCNT clock domain is not updated with the new written value.
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318
Bit Position
Bit Position
Underflow Interrupt Enable
I/O Location
Register Update Freeze
Description
Description
Description
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