EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 44

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-09-06 - d0001_Rev1.00
alternate to primary… until it reads a data structure that is invalid, or until the host processor disables
the channel.
Figure 8.3 (p. 44) shows an example of a ping-pong DMA transaction.
Figure 8.3. Ping-pong example
In Figure 8.3 (p. 44) :
Task A
After task A completes, the host processor can configure the primary data structure for task C. This
enables the controller to immediately switch to task C after task B completes, provided that a higher
priority channel does not require servicing.
After the controller receives a new request for the channel and it has the highest priority then task B
commences:
Task A: Prim ary, cycle_ctrl = b011, 2
Task B: Alternate, cycle_ctrl = b011, 2
Task C: Prim ary, cycle_ctrl = b011, 2
Task D: Alternate, cycle_ctrl = b011, 2
Task E: Prim ary, cycle_ctrl = b011, 2
End: Alternate, cycle_ctrl = b000
1. The host processor configures the primary data structure for task A.
2. The host processor configures the alternate data structure for task B. This enables the
3. The controller receives a request and performs four DMA transfers.
4. The controller arbitrates. After the controller receives a request for this channel, the flow
5. The controller performs the remaining two DMA transfers.
6. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
controller to immediately switch to task B after task A completes, provided that a higher
priority channel does not require servicing.
continues if the channel has the highest priority.
arbitration process.
Request
Request
Request
Request
Request
R
R
R
R
= 4, N = 7
= 4, N = 6
= 2, N = 2
R
Request
Request
Request
Request
Request
= 4, N = 12
= 4, N = 5
Task A
Task C
Task E
Task B
Task D
Invalid
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