EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 200

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.2 USARTn_FRAME - USART Frame Format Register
2
1
0
31:14
13:12
11:10
9:8
Bit
Offset
0x004
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Multi-processor mode uses the 9th bit of the USART frames to tell whether the frame is an address frame or a data frame.
CCEN
Enables collision checking on data when operating in half duplex modus.
LOOPBK
Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication.
SYNC
Determines whether the USART is operating in asynchronous or synchronous mode.
Reserved
STOPBITS
Determines the number of stop-bits used.
Reserved
PARITY
Determines whether parity bits are enabled, and whether even or odd parity should be used. Only available in asynchronous mode.
Name
Name
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Value
0
1
2
3
Value
0
2
3
Mode
HALF
ONE
ONEANDAHALF
TWO
Mode
NONE
EVEN
ODD
Description
The 9th bit of incoming frames has no special function
An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and
will result in the MPAB interrupt flag being set
Description
Collision check is disabled
Collision check is enabled. The receiver must be enabled for the check to be performed
Description
The receiver is connected to and receives data from U(S)n_RX
The receiver is connected to and receives data from U(S)n_TX
Description
The USART operates in asynchronous mode
The USART operates in synchronous mode
0
0
0
0x1
0x0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
Access
Access
Description
The transmitter generates a half stop bit. Stop-bits are not verified by receiver
One stop bit is generated and verified
The transmitter generates one and a half stop bit. The receiver verifies the first stop bit
The transmitter generates two stop bits. The receiver checks the first stop-bit only
Description
Parity bits are not used
Even parity are used. Parity bits are automatically generated and checked by hardware.
Odd parity is used. Parity bits are automatically generated and checked by hardware.
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200
Bit Position
Collision Check Enable
Loopback Enable
USART Synchronous Mode
Stop-Bit Mode
Parity-Bit Mode
Description
Description
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