EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 158

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.9.4 Slave Receiver
2010-09-06 - d0001_Rev1.00
Table 15.8. I
A slave receiver operation is started in the same way as a slave transmitter operation, with the exception
that the address transmitted by the master has the R/W bit cleared (W), indicating that the master wishes
to write to the slave. The slave then goes into slave receiver mode.
To receive data from the master, the slave should respond to the address with an ACK and make sure
space is available in the receive buffer. Transmission will then continue, and the slave will receive a
byte from the master.
If a NACK is sent without a CONT, the transmission is ended for the slave, and it goes idle. If the slave
issues both the NACK and CONT commands and has space available in the receive buffer, it will be
open for continuing reception from the master.
When a byte has been received from the master, the slave must ACK or NACK the byte. The responses
here are the same as for the reception of the address byte.
The master ends the transmission by sending a STOP or a repeated START. The SSTOP interrupt flag
is set when the master transmits a STOP condition. If the transmission is ended with a repeated START,
then the SSTOP interrupt flag in I2Cn_IF is not set.
Note
If arbitration is lost at any time during transmission, the ARBLOST interrupt flag in I2Cn_IF is set, the
bus is released and the slave goes idle.
I2Cn_STATE Description
0x41
0x73
-
0xD5
0xDD
-
-
The SSTOP interrupt flag in I2Cn_IF will be set regardless of whether the slave is
participating in the transmission or not, as long as SLAVE in I2Cn_CTRL is set and a STOP
condition is detected
Repeated START
received
ADDR + R received
Data transmitted
Data transmitted, ACK
received
Data transmitted,
NACK received
Stop received
Arbitration lost
2
C Slave Transmitter
I2Cn_IF
RSTART interrupt flag
(BUSHOLD interrupt
flag)
ADDR interrupt flag
RXDATA interrupt flag
(BUSHOLD interrupt
flag)
TXBL interrupt flag
(TXC interrupt flag)
ACK interrupt flag
(BUSHOLD interrupt
flag)
NACK interrupt flag
(BUSHOLD interrupt
flag)
SSTOP interrupt flag
ARBLOST interrupt
flag
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158
Required
interaction
RXDATA
ACK +
TXDATA
NACK
NACK +
CONT +
TXDATA
None
TXDATA
None
CONT +
TXDATA
None
START
None
START
Response
Receive and compare address
ACK will be sent, then DATA
NACK will be sent, slave goes idle
NACK will be sent, then DATA.
DATA will be transmitted
The slave goes idle
DATA will be transmitted
The slave goes idle
START will be sent when bus becomes idle
The slave goes idle
START will be sent when the bus becomes idle
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