EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 244

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.3.1 Counter Modes
19.3.1.1 Events
19.3.1.2 Operation
2010-09-06 - d0001_Rev1.00
Figure 19.1. TIMER Block Overview
The Timer consists of a counter that can be configured to the following modes:
1. Up-count: Counter counts up until it reaches the value in TIMERn_TOP, where it is reset to 0 before
2. Down-count: The counter starts at the value in TIMERn_TOP and counts down. When it reaches 0,
3. Up/Down-count: The counter starts at 0 and counts up. When it reaches the value in TIMERn_TOP,
4. Quadrature Decoder: Two input channels where one determines the count direction, while the other
The counter value can be read or written by software at any time by accessing the CNT field in
TIMERn_CNT.
Overflow is set when the counter value shifts from TIMERn_TOP to the next value when counting up. In
up-count mode the next value is 0. In up/down-count mode, the next value is TIMERn_TOP-1.
Underflow is set when the counter value shifts from 0 to the next value when counting down. In down-
count mode, the next value is TIMERn_TOP. In up/down-count mode the next value is 1.
Update event is set on overflow in up-count mode and on underflow in down-count or up/down count
mode. This event is used to time updates of buffered values.
Figure 19.2 (p. 245) shows the hardware Timer/Counter control. Software can start or stop the counter
by writing a 1 to the START or STOP bits in TIMERn_CMD. The counter value (CNT in TIMERn_CNT)
can always be written by software to any 16-bit value.
It is also possible to control the counter through either an external pin or PRS input. This is done through
the input logic for the Compare/Capture Channel 0. The Timer/Counter allows individual actions (start,
stop, reload) to be taken for rising and falling input edges. This is configured in the RISEA and FALLA
fields in TIMERn_CTRL. The reload value is 0 in up-count and up/down-count mode and TOP in down-
count mode.
counting up again.
it is reloaded with the value in TIMERn_TOP.
it counts down until it reaches 0 and starts counting up again.
pin triggers a clock event.
TIMn_CC0
TIMn_CC1
TIMn_CC2
HFPERCLK
PRS inputs
PRS inputs
PRS inputs
TIMERn
Input logic
Input logic
Input logic
Quadrature
Decoder
Prescaler
detect
detect
detect
Edge
Edge
Edge
CNTCLK
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Input Capture
244
TnCCR0[ 15:0
TnCCR1[ 15:0
TIMERn_CNT
TIMERn_CCx
Counter
control
]
]
condition
Update
= =
=
TIMERn_TOP
= 0
=
Com pare and
Com pare and
Com pare and
PWM config
PWM config
PWM config
Note: For sim plicity, all
TIMERn_CCx registers are
grouped together in the figure,
but they all have individual Input
Capture Registers
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Overflow
Underflow
Com pare Match x
TIMn_CC1
TIMn_CC2
TIMn_CC0