EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 441

MCU 32BIT 64KB FLASH 32-QFN

EFM32G200F64

Manufacturer Part Number
EFM32G200F64
Description
MCU 32BIT 64KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F64

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number
Manufacturer
Quantity
Price
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Part Number:
EFM32G200F64-QFN32
Quantity:
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29.5.18 LCD_SEGD2H - Segment Data High Register 2 (Async Reg)
29.5.19 LCD_SEGD3H - Segment Data High Register 3 (Async Reg)
31:8
7:0
31:8
7:0
31:8
7:0
Bit
Offset
0x058
Reset
Access
Name
Bit
Offset
0x05C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
SEGD1H
This register contains segment data for segment lines 32-39 for COM1.
Reserved
SEGD2H
This register contains segment data for segment lines 32-39 for COM2.
Reserved
SEGD3H
This register contains segment data for segment lines 32-39 for COM3.
Name
Name
Name
0x00
0x00
0x00
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
Access
Access
Access
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441
Bit Position
Bit Position
COM1 Segment Data High
COM2 Segment Data High
COM3 Segment Data High
Description
Description
Description
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