EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 134

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.3.2 16-bit Address Mode
2010-09-06 - d0001_Rev1.00
In this mode, 16-bit address and 16-bit data is supported, which requires the utilization of a latch. An
illustration of such a setup is shown in Figure 14.4 (p. 134)
Note
Figure 14.4. EBI Address Latch Setup
At the start of the transition the address is output on the EBI_AD lines. The Latch is controlled by the
ALE (Address Latch Enable) signal and stores the address. Then the data is read or written according
to operation. Read and write signals are shown in Figure 14.5 (p. 134) and Figure 14.6 (p. 134)
respectively.
Figure 14.5. EBI 16-bit Read Operation
Figure 14.6. EBI 16-bit Write Operation
EBI_AD[ 15:0]
EBI_WEn
EBI_CSn
In this mode the 16-bit address is organized in 2-byte chunks at memory addresses aligned
to 2-byte offsets. Consequently, the LSB of the 16-bit address will always be 0. In order to
double the address space, the 16-bit address is internally shifted one bit to the right so that
the LSB of the address driven into the EBI_AD bus, i.e. the EBI_AD[0]-bit, corresponds to
the second least significant bit of the address, i.e. ADDR[1]. At the external device, the LSB
of the address must be tied either low or high in order to create a full address.
EBI_ALE
EBI_AD[ 15:0]
EBI_CSn
EBI_REn
EBI_ALE
(EFM32)
EBI
ADDRSET
ADDR[ 15:0]
ADDRSET
ADDR[ 15:0]
ADDRHOLD
EBI_AD
RDSETUP
...the world's most energy friendly microcontrollers
ALE
134
Latch
WRSETUP
Z
RDSTRB
Control
ADDR
DATA
DATA[ 15:0]
DATA[ 15:0]
WRSTRB
RDHOLD
External
Async.
Device
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WRHOLD
Z
Z