EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 147

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.4 Clock Generation
15.3.5 Arbitration
2010-09-06 - d0001_Rev1.00
I2Cn_CTRL must be reset. This should be done regardless whether the slave is going to be re-enabled
or not.
The SCL clock signal generated by the I
The clock is generated as a division of the peripheral clock, and is given by Equation 15.2 (p. 147) :
I
N
signal respectively. The worst case low and high periods of the signal are:
I
The values of N
controlled by CLHR in the I2Cn_CTRL register. The available modes are summarized in Table 15.2 (p.
147) along with the highest I
violating the timing specifications of the I
allowed rise and fall times of SDA and SCL into account. Higher frequencies may be achieved in
practice. The 3 extra cycles are synchronization, and must be taken into consideration when DIV in the
I2Cn_CLKDIV register has a low value.
Note
Table 15.2. I
Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When
arbitration is enabled, the value on SDA is sensed after each time the I
its value. If the sensed value is different than the value the I
a simultaneous transmission by another device, and the I
Whenever arbitration is lost, the ARBLOST interrupt flag in I2Cn_IF is set, any lines held are released,
and the I
another master may be trying to address it. The master therefore receives the rest of the address, and
if the address matches the slave address of the master, the master goes into either slave transmitter
or slave receiver mode.
Note
2
2
Mode
STANDARD
ASYMMETRIC
FAST
C Maximum Transmission Rate
low
C High and Low Cycles Equations
and N
2
C device goes idle. If an I
DIV must be 1 or higher when slave is enabled.
Arbitration can be lost both when operating as a master and when operating as a slave.
high
2
C Clock Modes
specify the number of prescaled clock cycles in the low and high periods of the clock
low
CLHR
0
1
2
and N
f
SCL
high
= f
T
T
high
low
HFPERCLK
and thus the ratio between the high and low parts of the clock signal is
2
C-bus frequencies in the given modes that can be achieved without
= (N
= (N
N
4:4
6:3
11:6
2
low
high
low
C master loses arbitration during the transmission of an address,
/(((N
: N
x (DIV + 1)+ 3)/f
x (DIV + 1) + 3)/f
2
C master determines maximum transmission rate on the bus.
high
2
C-bus. The frequencies are calculated taking the maximum
low
+ N
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147
high
Sm max
frequency
93 kHz
75 kHz
79 kHz
) x (DIV + 1)) + 4)
HFPERCLK
HFPERCLK
2
C module has lost arbitration.
2
C module tried to output, it is interpreted as
Fm max
frequency
313 kHz
392 kHz
383 kHz
2
C module attempts to change
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Fm+ max
frequency
806 kHz
980 kHz
987 kHz
(15.2)
(15.3)