EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 232

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.3 LEUARTn_STATUS - Status Register
18.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg)
31:6
5
4
3
2
1
0
31:15
14:3
2:0
Bit
Offset
0x008
Reset
Access
Name
Bit
Offset
0x00C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Set to activate data reception on LEUn_RX.
Reserved
RXDATAV
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
TXBL
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
TXC
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmission starts.
RXBLOCK
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the
instant the frame has been completely received.
TXENS
Set when the transmitter is enabled.
RXENS
Set when the receiver is enabled. The receiver must be enabled for start frames, signal frames, and multi-processor address bit
detection.
Reserved
DIV
Specifies the fractional clock divider for the LEUART.
Reserved
Name
Name
Name
0
1
0
0
0
0
0x000
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
R
R
R
RW
Access
Access
Access
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232
Bit Position
Bit Position
RX Data Valid
TX Buffer Level
TX Complete
Block Incoming Data
Transmitter Enable Status
Receiver Enable Status
Fractional Clock Divider
Description
Description
Description
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