EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 347

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.3.7.8 Adjustment
25.3.8 Interrupts, PRS Output
25.3.9 DMA Request
25.3.10 Calibration
2010-09-06 - d0001_Rev1.00
By default, all results are right adjusted, with the LSB of the result in bit position 0 (zero). In differential
mode the signed bit is extended up to bit 31, but in single ended mode the bits above the result are read
as 0. By setting ADJ in ADCn_SINGLECTRL/ADCn_SCANCTRL, the results are left adjusted as shown
in Table 25.4 (p. 347) . When left adjusted, the MSB is always placed on bit 15 and sign extended to
bit 31. All bits below the conversion result are read as 0 (zero).
Table 25.4. ADC Results Representation
The single and scan modes have separate interrupt flags indicating finished conversions. Setting one of
these flags will result in an ADC interrupt if the corresponding interrupt enable bit is set in ADCn_IEN.
In addition to the finished conversion flags, there is a scan and single sample result overflow flag which
signalizes that a result from a scan sequence or single sample has been overwritten before being read.
A finished conversion will result in a one HFPERCLK cycle pulse which is output to the Peripheral Reflex
System (PRS).
The ADC has two DMA request lines, SINGLE and SCAN, which are set when a single or scan
conversion has completed. The request are cleared when the corresponding single or scan result register
is read.
The ADC supports offset and gain calibration to correct errors due to process and temperature variations.
This must be done individually for each reference used. The ADC calibration (ADCn_CAL) register
contains four register fields for calibrating offset and gain for both single and scan mode. The gain and
offset calibration are done in single mode, but the resulting calibration values can be used for both single
and scan mode.
Gain and offset for the 1V25, 2V5 and VDD references are calibrated during production and the
calibration values for these can be found in the Device Information page. During reset, the gain and
offset calibration registers are loaded with the production calibration values for the 1V25 reference.
The SCANGAIN and SINGLEGAIN calibration fields are not used when the unbuffered differential
2xVDD reference is selected.
OVS 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 14 13 12 11 10 9
OVS 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 14 13 12 11 10 9
12 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 9
12 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 9
8
6
8
6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
...the world's most energy friendly microcontrollers
347
7
5
7
5
7
5
7
5
Bit
7
5
7
5
7
5
6
4
7
5
5
3
7
5
8
4
2
7
5
7
3
1
7
5
6
2
0
7
5
5
1
-
8
8
7
5
8
4
0
8
-
www.energymicro.com
7
7
7
5
7
3
7
-
-
6
6
6
5
6
2
6
-
-
5
5
5
5
5
1
5
-
-
4
4
4
4
4
0
4
-
-
3
3
3
3
3
3
-
-
-
2
2
2
2
2
2
-
-
-
1
1
1
1
1
1
-
-
-
0
0
0
0
0
0
-
-
-