EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 151

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.7.2.1 Automatic ACK Interaction
15.3.7.3 Reset State
15.3.7.4 Master Transmitter
2010-09-06 - d0001_Rev1.00
set in a pending state, which can be read from the STATUS register. A pending START command can
for instance be identified by PSTART having a high value.
Whenever the I
combination of these can fulfill an interaction, they are consumed by the module and the transmission
continues without setting the BUSHOLD interrupt flag in I2Cn_IF to get an interaction from software.
The pending status of a command goes low when it is consumed.
When several interactions are possible from a set of pending commands, the interaction with the highest
priority, i.e. the interaction closest to the top of Table 15.3 (p. 150) is applied to the bus.
Pending commands can be cleared by setting the CLEARPC command bit in I2Cn_CMD.
When receiving addresses and data, an ACK command in I2Cn_CMD is normally required after each
received byte. When AUTOACK is set in I2Cn_CTRL, an ACK is always pending, and the ACK-pending
bit PACK in I2Cn_STATUS is thus always set, even after an ACK has been consumed. This can be used
to reduce the amount of software interaction required during a transfer.
After a reset, the state of the I
a reset of the I
reset, and the BUSY flag in I2Cn_STATUS is thus set. To be able to carry through master operations
on the I
The bus goes idle when a STOP condition is detected on the bus, but on buses with little activity, the
time before the I
that the I
• Use the ABORT command in I2Cn_CMD. When the ABORT command is issued, the I
• Use the Bus Idle Timeout. When SCL has been high for a long period of time, it is very likely that the
Note
To transmit data to a slave, the master must operate as a master transmitter. Table 15.4 (p. 152)
shows the states the I
an interaction is required has the possible interactions listed, along with the result of the interactions.
The table also shows which interrupt flags are set in the different states. The interrupt flags enclosed
in parenthesis may be set. If the BUSHOLD interrupt in I2Cn_IF is set, the module is waiting for an
interaction, and the bus is frozen. The value of I2Cn_STATE will be equal to the values given in the table
when the BUSHOLD interrupt flag is set, and can be used to determine which interaction is required to
make the transmission continue.
The interrupt flag START in I2Cn_IF is set when the I
A master operation is started by issuing a START command by setting START in I2Cn_CMD. ADDR
+W, i.e. the address of the slave to address + the R/W bit is then required by the I
is not available in the transmit buffer, then the bus is held and the BUSHOLD interrupt flag is set. The
instructed that the bus is idle. The I
bus is idle. Set BITO in I2Cn_CTRL to an appropriate timeout period and set GIBITO in I2Cn_CTRL.
If activity has not been detected on the bus within the timeout period, the bus is then automatically
assumed idle, and master operations can be initiated.
2
C-bus, the bus must be idle.
2
C module gets out of the busy state.
If operating in slave mode, the above approach is not necessary.
2
C module or the entire MCU, the I
2
2
C module detects that the bus is idle can be significant. There are two ways of assuring
C module requires an interaction, it checks the pending commands. If one or a
2
C module goes through while acting as a master transmitter. Every state where
2
C-bus is unknown. To avoid interrupting transfers on the I
2
C module can then initiate master operations.
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2
C-bus is assumed to be busy when coming out of a
2
C module transmits the START.
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2
C module. If this
2
2
C module is
C-bus after